The present invention relates to a distributed clocking mechanism for a distributed synchronous processing system, and more particularly, to a distributed clocking mechanism particularly useful for a distributed digital telephone switching network.
Distributed synchronous processing systems, e.g., those used in large digital telecommunication switching networks, typically require extremely accurate clocking systems to synchronize the various time related operations performed among a plurality of switching stages and their controllers. The clocking signals in such systems generally originate from a centralized clocking source that generates and transmits the clocking signals throughout the system over a dedicated clocking signal transmission network.
Although such clocking schemes are satisfactory for many applications, they suffer from a number of weaknesses. In particular, the reliance on a centralized clocking source leaves a distributed processing system susceptible to system-wide failures in the event of a malfunction in the clocking center. The dependence on a single centralized clock source may be minimized by utilizing a set of redundant clock sources. In such a system, there is a centralized clocking center having a set of clocks that generate and transmit a group of redundant clock signals throughout the network.
A system with this type of arrangement is the International Telephone and Telegraph (I.T.T.) System 12 (now produced by Alcatel). The System 12 uses a pair of reliable clock sources that are distributed by means of a separate clocking signal transmission network comprised of 2 continuous loops (one for each clock source). Each multi-port switch element in the System 12 is coupled to both clock distribution loops and includes a clock selection circuit for selecting one of the two available system clock signals for synchronizing its internal operations. The clock selection circuitry allows a switchover to the alternate clock when a degradation is detected in the currently selected clock signal. This system, however, has experienced problems associated with the distribution of the clocking signals. In particular, since each clock distribution loop is essentially a continuous conductor, a failure in any portion of one of the loops will entirely interrupt the distribution of the associated clock source; thereby leaving the System 12 without an alternate clock signal.
The clock sources in the System 12 must often act as slaves to clock signals derived from external sources such as the national digital network. In such a case, the System 12 is often connected to the national digital network by means of a number of external digital transmission links. Since it is desirable to synchronize to only one of the clock signals associated with these national network digital transmission links at any given time, the System 12 ranks the clock signals of the national network according to the rank of the associated Central Office and the grade of the particular transmission link. The ranking allows the best available clock to be selected for synchronizing the operations of the System 12. The System 12 ranking scheme is implemented in hardware by directly wiring the System 12 clocks to each of the highest ranked clock signals of the national network. As can be seen, the re-ranking of the clock sources in the System 12, as is often required in dynamic switching networks of this type, requires the movement of wires from one national network digital transmission link to another.
Other solutions that have been attempted suffer from similar deficiencies. Elastic buffer arrangements have been utilized to synchronize outgoing transmissions in switch elements having a number of unsynchronized inputs with unaligned phases. The elastic buffers write data into the buffer and read it out of the buffer with two independent clock signals, in order to adjust the unaligned incoming data signals so that the output signals are phase-aligned with one another. Problems in systems utilizing an elastic buffer arrangement have resulted because the two clock signals used to write into and read out of the buffer are not frequency synchronized which can often result in a frame slip (the loss or duplication of an entire frame).